Statistical Characterization of Standard Cells for Variation Aware Delay Modeling

With the advance in CMOS VLSI circuit design through technology scaling, process variability has significantly increased uncertainties in the response of sub-45nm CMOS circuits. To address this challenge and obtain reliable fabricated chips, statistical timing analysis and library characterization tools have become significantly important. CPU-time intensive Monte Carlo (MC) simulations embedded on circuit simulators become the most accurate approach for statistical characterization of standard cell libraries. However, such approaches require a prohibitive number of electrical simulations for a full library characterization. The challenge is thus to achieve near MC accuracy with a limited set of simulations. This papers looks at some interesting approaches proposed in literature. It discusses the state-of-the-art in statistical library characterization as well as surveys more advanced techniques such as Statistical-Design of Experiments for reducing the number of Monte Carlo simulations.